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4318_4318e-ds01-405-r 16215 alton parkway ? p.o. box 57013 ? irvine, california 92619-7013 ? phone: 949-450-8700 ? fax: 949-450-8710 11/09/04 preliminary data sheet bcm4318/bcm4318e airforce one? chip 802.11g mac/baseband/radio figure 1: bcm4318/bcm4318e system diagram general description features the bcm4318/bcm4318e provide one chip ieee 802.11g mac, baseband, and direct conversion radio functions to provide wireless lan connectivi ty supporting data rates from 1 mbps to 54 mbps in the 2.4-ghz band. with the addition of the bcm2060, the solution can also support 802.11a for 1-mbps to 54-mbps connectivity in the 5-ghz band. in addition, the bcm4318e includes leading-edge encore dsp technology for best-in-class receive sensitivity and extended range, enabling whole home coverage. the bcm4318e also supports high- speed performance mode (125-mbps) that is backward- compatible with standard 802.11b/g. broadcom?s revolutionary one chip architecture implemented in bulk cmos process greatly reduces the external components typically required for 802.11a/g implementations, resulti ng in significant cost, power, and footprint savings. state-of-the-art security is provided by industry standardized system support for wep, wep2, and aes encryption, coupled with tkip and ieee 802.1x support. increased performance and a significant reduction in host-cp u utilization in both client and access device configurations are achieved through hardware support of encryption/decryption. the bcm4318/bcm4318e employ a native 32-bit bus using a direct memory access architecture that results in significant performance improvements over competing solutions in both transfer rate and cpu utilization. various system bus interfaces are included for maximum flexibil ity: mini pci, pci, cardbus, pcmcia/compact flash, and sdio/spi. the bcm4318/bcm4318e employ adaptive equalization algorithms resulting in significant resistance to multipath, providing substantial improvemen ts in real-world performance. ? extreme integration: ieee 802.11a/g compliant cmos mac / baseband and 2.4-ghz direct conversion radio (802.11a radio support provided by an external bcm2060 5-ghz direct conversion radio) ? bcm4318e includes encore signal processing for industry- leading receive sensitivity and extended range: - ?74 dbm at 54mbps - ?76 dbm with external lna ? high level of integration with direct conversion radio architecture minimizes external circuitry, leading to lowest cost, lowest power, and smallest footprint implementation ? flexible support for a variety of system bus interfaces including: pci, mini pci, cardbus, pcmcia/compact flash, and sdio (4-wire, 1-wire, and spi) ? programmable data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54 mbps ? supports high-speed performance mode of 125-mbps that is backward-compatible with standard 802.11b/g; bcm4318e in 196-pin package supports afterburner mode (125-mbps) ? 24-bit iv and 40-bit/104-bit key wep encryption support ? 128-bit iv and 128-bit key wep2 encryption support ? system support for 128-bit aes ? ieee 802.1x support ? programmable mac with advanced dma architecture and 32-bit bus interface ? dynamic power management under driver control ? whql-certified drivers for windows ? xp, windows ? me, windows ? 2000, windows ? 98se, and windows ? 98 operating systems ? all drivers are portable for embedded operating systems such as linux ? and windows ? ce ? meets pci power management interface version 1.1 (acpi) ? wi-fi ? compliant; supports secureezsetup? ? support for bluetooth ? coexistence algorithm ? 3.3/1.8v supply, 3/5v pci i/o ? 144-ball fbga or 196-ball fb ga (adds uart, pci/cardbus and bcm2060 interfaces) 20mhz power amp t/r switch balun balun 802.11a/g bb mac buffers host i/f: cf, sdio, pcmcia, pci 2.4 ghz cmos direct conversion radio bcm4318 wep/aes encryption sprom lpf lpf host i/f gpio 1.8v 3.3v bcm2060 and fe (optional .11a) 20 mhz power amp diversity switch t/r switch balun balun 802.11a/g bb mac buffers host i/f: cf, sdio, pcmcia, pci 2.4 ghz cmos direct conversion radio bcm4318/bcm4318e wep/aes encryption sprom lpf lpf host i/f gpio 1.8v 3.3v bcm2060 and fe (optional .11a)
broadcom ? , the pulse logo, airforce one?, and secureezset up? are trademarks of br oadcom corporation and/or its subsidiaries in the united states and certain other countries. bluetooth ? is a trademark of the bluetooth sig. all other trademarks mentioned are the propert y of their respective owners. this data sheet (including, without limit ation, the broadcom compon ent(s) identified herein) is not designed, intended, or certified for use in any military, nuclear, medical, mass transportation, aviation, navigations, pollution control, hazardous substances management, or other high risk application. broadcom provides this data sheet "as- is", without warranty of any kind. broadcom disclaims all warranties, expressed and implied, including, without li mitation, the implied warranti es of merchantabil ity, fitness for a particular purpose, and non-infringement. broadcom corporation p.o. box 57013 16215 alton parkway irvine, california 92619-7013 ? 2004 by broadcom corporation all rights reserved printed in the u.s.a. r evision h istory revision date change description 4318_4318e-ds01-r 11/09/04 updated esd value in table 13 on page 36. 4318_4318e-ds00-r 10/26/ 04 initial release.
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r page iii t able of c ontents section 1: functional description ............... ................. .............. .............. .............. ............1 introduction ............................................................................................................................... ................... 1 ieee 802.11a/g mac features.................................................................................................... ........... 2 ieee 802.11a/g mac description ................................................................................................. .......... 2 ieee 802.11a/g phy features .................................................................................................... ........... 4 ieee 802.11a/g phy description ................................................................................................. .......... 4 integrated radio transceiver ...................................................................................................................... 5 receiver path ............................................................................................................................... ................ 6 transmitter path ............................................................................................................................... ............ 7 calibration ............................................................................................................................... ..................... 7 crystal oscillator ............................................................................................................................... .......... 7 section 2: pin assignments ................ ................ ................. ................ ................. ..............9 144-pin bga assignments .......................................................................................................................... 9 196-pin bga assignments ........................................................................................................................ 11 section 3: signal descriptions ................ ................ ................ ................. .............. .......... 14 144-pin bga descriptions ......................................................................................................................... 14 196-pin bga descriptions ......................................................................................................................... 20 strapping options ............................................................................................................................... ....... 30 sdio pin descriptions ............................................................................................................................... 31 section 4: electri cal characteristics .............. .............. .............. .............. .............. .......... 34 recommended operating conditions ...................................................................................................... 34 current consumption ............................................................................................................................... .35 local oscillator specifications ................................................................................................................. 36 environmental characteristics ................................................................................................................. 36 section 5: rf specifications ............... ................ ................. ................ ................. ............ 37 general rf specifications ......................................................................................................................... 37 receiver rf specifications ....................................................................................................................... 37 transmitter rf specifications .................................................................................................................. 38 section 6: timing characteristics ............... ................. .............. .............. .............. .......... 39 pcmcia/compact flash timing ................................................................................................................ 39
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page iv document 4318_4318e-ds01-405-r sprom timing ............................................................................................................................... ............. 42 jtag timing ............................................................................................................................... ................ 43 section 7: package specifications ................. .............. .............. .............. .............. ......... 44 section 8: ordering information ................ ................. .............. .............. .............. ........... 46
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r page v l ist of f igures figure 1: bcm4318/bcm4318e system diagram ...................................................................................... .........i figure 2: ieee 802.11a/g mac bl ock diagram......... ................. ................ ................ ................ ........... ............. 3 figure 3: ieee 802.11a/g phy bl ock diagram ......... ................. ................ ................ ................ ........... ............. 5 figure 4: radio functional block diagram ....................................................................................... .................. 6 figure 5: recommended oscillator configuration..... ............................................................................ ............. 8 figure 6: bcm4318/bcm4318e 144-pin top view assignments ...................................................................... 9 figure 7: bcm4318/bcm4318e 196-pin top view assignments .................................................................... 11 figure 8: signal connecti ons to sdio card (sd 4-bit mode) ...................................................................... .... 31 figure 9: signal connecti ons to sdio card (sd 1-bit mode) ...................................................................... .... 32 figure 10: signal connections to sdio card (spi mode).......................................................................... ...... 32 figure 11: signal connections to pcmcia/compact flash .......................................................................... ... 33 figure 12: pcmcia/compact flash read timing diagram ............................................................................ .39 figure 13: pcmcia/compact flash write timing diagr am ........................................................................... .. 41 figure 14: bcm4318/bcm4318e 14 4-pin fbga....................................................................................... ...... 44 figure 15: bcm4318/bcm4318e 19 6-pin fbga....................................................................................... ...... 45
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page vi document 4318_4318e-ds01-405-r
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r page vii l ist of t ables table 1: differences among bcm4318 /bcm4318e and 144-pin/196-pin packages ........................................ 1 table 2: 20-mhz crystal requirements .............. ............................................................................. .................. 7 table 3: 144-pin assignments................................................................................................... ......................... 9 table 4: 196-pin assignments................................................................................................... ....................... 12 table 5: bcm4318/bcm4318e 144-pin bga signal descriptions .................................................................. 14 table 6: bcm4318/bcm4318e 196-pin bga signal descriptions .................................................................. 20 table 7: sprom mode and size ................................................................................................... .................. 30 table 8: bus mode configuratio ns ............................................................................................... .................... 31 table 9: sdio pin descriptions................................................................................................. ....................... 31 table 10: recommended operating conditions ....... .............................................................................. ......... 34 table 11: current consumption .................................................................................................. ..................... 35 table 12: local oscillator specifications............. ......................................................................... .................... 36 table 13: environmental characteristics............. ........................................................................... .................. 36 table 14: general rf specifications................... ......................................................................... .................... 37 table 15: receiver rf specifications ........................................................................................... ................... 37 table 16: transmitter rf specifications ............. ........................................................................... .................. 38 table 17: pcmcia/compact flash read timing characte ristics .................................................................... 4 0 table 18: pcmcia/compact flash write timing characte ristics .................................................................... 42 table 19: sprom timing characteristics.............. ........................................................................... ............... 42 table 20: jtag timing characteri stics.......................................................................................... .................. 43 table 21: bcm4318/bcm4318e orderi ng information ................................................................................ .... 46
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page viii document 4318_4318e-ds01-405-r
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 1:functional description page 1 section 1: functional description i ntroduction the bcm4318/bcm4318e are highly integr ated, single-chip, ieee std 802.11a/ g mac, baseband and 2.4-ghz direct conversion radios designed for client cards, modules, and wombo (wireless on motherboard) solutions. the revolutionary broadcom ? one chip architecture greatly reduces the external components ty pically required for ieee 802.11a/g implementations, resulting in significant savings in cost, power, and board space. the bcm4318/bcm4318e offer flex ible support for a variety of system bus interfaces incl uding pci, mini pci, cardbus, pcmcia, compact flash, and sdio/spi. customer-specified pa rameters, such as system vendor id and wireless lan mac address, are stored in a small external sprom. in addition, the bcm4318e chip includes leading-edge encore dsp technology for improved receive sensitivity, which extends the range and enables whole home coverage. the bcm4318e chip also supports a uart interface for wlan design support. the package options are 144 pin and 196 pin, as follows: ? the bcm4318 chip in the 196-pin package adds pci, cardbu s, and bcm2060 ieee 802.11a radio interfaces, but does not support encore dsp technology. ? the bcm4318e chip in the 196-pin package adds pci, ca rdbus, and bcm2060 ieee 802.11a radio interfaces. it includes encore dsp technology, and it supports a uart interface. ? the bcm4318e chip in the 144-pin package provides pcmc ia, compact flash, and sdio/spi bus interfaces. it includes encore dsp technology. table 1 lists differences between the bcm4318 and bcm 4318e chips and between the 144-pin and 196-pin packages. table 1: differences among bcm4318/ bcm4318e and 144-pin/196-pin packages chip package (mini) pci cardbus pcmcia compact flash sdio/ spi sprom gpio ieee 802.11a phy encore and after- burner bcm4318 196-pin bcm4318kfbg yes yes yes yes sdio/ spi yes 8 yes ? bcm4318e 196-pin BCM4318EKFBG yes yes yes yes sdio/ spi/ uart 1 yes 8 yes encore and after- burner bcm4318e 144-pin bcm4318skfbg ? ? yes yes sdio/ spi yes 6 ? encore notes: 1. the uart option is only available in t he bcm4318e 196-pin package option, BCM4318EKFBG.
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 2 section 1:functional desc ription document 4318_4318e-ds01-405-r ieee 802.11 a / g mac f eatures the ieee 802.11a/g ma c features include: ? programmable access point (ap) or station (sta) functionality ? programmable independent basic service set (ibss), or infrastructure mode ? passive scanning, 802.11h (including radio detection) ? network allocation vector (nav), inte rframe space (ifs), and timing synchronization function (tsf) functionality ? backoff ? rts/cts procedure ? transmission of response frames (ack/cts) ? address filtering of rx frames as specified by ibss rules ? multirate support ? programmable target beacon transmission time (tbtt) , beacon transmission/cancellation, and programmable announcement traffic indication message (atim) window ? cf conformance: setting nav for neighborhood point coordination function (pcf) operation ? privacy through a variety of wired equivalent privacy (wep) encryption schemes and dynamically programmable wep keys ? power management ? statistics counters for mib support ieee 802.11 a / g mac d escription the mac core provides the support requi red for the transmission and reception of sequences of packets, together with related timing, without any packet-by-packet driver interaction. time-critical tasks requiring response times of only a few milliseconds are handled in the mac core. this achieves th e required timing on the medium while keeping the host driver easier to write and maintain. also, incoming packets are buffered in the mac core, which allows the mac driver to process them in bursts as and when it gets access to the buffers. the mac driver interacts with the mac core to prepare queues of packets to transmit and to analyze and forward received packets. the internal blocks of the mac core are connect ed to a programmable state machine (psm) through an internal bus. see figure 2.
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 1:functional description page 3 figure 2: ieee 802.11 a/g mac block diagram the host interface consists of registers for controlling and m onitoring the status of the mac core and interfacing with the tx/rx fifos. there are four transmit fifos: asynchronous, priority, broadcast/multicast (bc/mc) and atim. each transmit fifo is 3-kb deep. in addition to the trans mit fifos, there is a 1-kb template area for response frames. whenever the host has a frame to transmit, the host queues t he frame into one of the transmit fifos wit h a tx descriptor containing tx control information. the psm schedules the transmission on the medi um depending on the frame type, transmission rules in ieee 802.11 protocol, and the current medium occupancy scenario. af ter the transmission is completed and an ack is received, a tx status is returned to the host conf irming the same in the tx status fifo. the mac contains a single 4.5-kb rx fifo . whenever a frame is received, the fram e is sent to the host along with an rx descriptor that contains additional informa tion about the frame reception conditions. the power management block maintains the information r egarding the power management st ate of the core (and the associated stas in case of an ap) to help in dynamic decisions by the core regarding frame transmission. the wep block performs the required wep operation on the tx /rx frames. the wep block supp orts separate transmit and receive keys with four shared keys and 50 link-specific keys. the link-specific ke ys are used to establish a secure link between any two stas, with the requir ed key being shared between only those two stas, hence excluding all the other stas in the same network from deciphering the communic ation between those two stas. the wep block supports the following encryption schemes that can be selected on a per-destination basis: ? none: the wep block acts as a pass-through ? wep: 40-bit secure key and 24-bit iv as defined in ieee std 802.11-1999 host interface (host registers) n tx fifos template 1 rx fifo wep / aes encryption power management programmable state machine (psm) data memory code memory timing and control phy interface tx status fifo tx engine rx engine
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 4 section 1:functional desc ription document 4318_4318e-ds01-405-r ? wep128: 104-bit secure key and 24-bit iv ? wep2: 128-bit secure key and 128-bit iv ? tkip: ieee 802.11i draft ? aes: ieee 802.11i draft the transmit engine is responsible for the byte flow from the tx fifo to the ph y interface through the wep block and the addition of an fcs (crc-32) as required by ieee 802.11. similarly, the receive engine is responsible for byte flow from the phy interface to the rx fifo through the wep blo ck and for detection of errors in the rx frame. the timing block performs the ts f, nav, and ifs functionality as described in ieee 802.11-1999. the programmable state machine (psm) coordinates the operation of different hard ware blocks required for both transmission and reception. the psm also maintain s the statistics counters required for mib support. ieee 802.11 a / g phy f eatures the integrated ieee 802.11a/g physical layer devi ce (phy) features include: ? data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54 mbps ? both long and optional short preamble ? resistance to multipath (>250 nanoseconds rms delay spread) with maximal ratio combining rake receiver for data rates of 1 and 2 mbps and adaptive equalization for data rates of 5.5 mbps and 11 mbps ? programmable antenna selection ? automatic gain control (agc) ? available per-packet channel quality and signal strength measurements ? dedicated interface to the bcm2060 5-ghz direct conversion radio for ieee 802.11a support ieee 802.11 a / g phy d escription the wireless local area network (wlan) phy integrated on this ic provides baseband processing at data rates of 1, 2, 5.5, 6, 9, 11, 12, 18, 24, 36, 48, and 54 mbps, as spec ified in the direct s equence spread spectrum (dsss) and orthogonal frequency division multiplexing (ofdm) portions of ieee 802.11 a/g. this core acts as an intermediary between the mac on the one hand, and the integrated 2.4-ghz radio or external 5-ghz radio (bcm2060) integrated circuit on the other, converting back and forth between packets and baseband waveforms. an overview of the operations carried out by the phy is shown in figure 3. on transmission, physical layer framing is first added to a packet received from the mac. the resulting bits are then scrambled, modulat ed, filtered, and finally sent to the rf via a pair of 80-mhz, 6-bit digital-to-analog converters (dac s). modulation is selected per packet as either differential binary phase shift keying (dbpsk), differential quadrature phase shift keying (dqpsk), or complementary code keying (cck). the first two types of modulation provide data rates of 1 mbps and 2 mbps, respectively, and require spreading the modulated symbols with a length 11 barker code. cck modulation is used for data rates of 5.5 mbps and 11 mbps and inherently includes the spreading.
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 1:functional description page 5 figure 3: ieee 802.11a/g phy block diagram on reception, the reverse operations are performed. the in-phase (i) and quadrat ure (q) baseband waveforms coming from a pair of 40-mhz, 6-bit analog-to-digital converters (adcs) are demodulated into bits and then descrambled and deframed. to improve the likelihood of correct reception, however, the waveforms are subjected to timing and frequency offset corrections (adapted throughout packet reception) prior to dem odulation. further, using a maximal ratio combining rake receiver for data rates of 1 mbps and 2 m bps and an adaptive equalizer at the higher bit rates, the phy is able to work in extreme multipath channels, successfully receiving even at a data rate of 11 mbps, with delay spreads exceeding 200 nanoseconds rms. additionally, the receiver must perform synchronization at the start of packet reception, which includes automatic gain control (agc), antenna selection, and initial frequency offset an d timing estimation. a state ma chine coordinates all of these activities (using information from the phy framing) to decide how to handle the packet body. a register interface accessible from both the mac and t he host allows programming of the phy parameters, although information generally needed per packet is passed as part of the packet itself. for example, this is true of preamble type and data rate on transmission, as well as the channel metrics si gnal quality (sq) and signal stre ngth on reception. the internal 2.4-ghz radio and bcm2060 registers are accessed indirectly through the phy registers. i ntegrated r adio t ransceiver the bcm4318/bcm4318e include an integrated rf transceiver that has been optimized for use in 2.4-ghz wireless lan systems. it has been designed to provide low-power, low-cost, and robust communications for applications operating in the tx fsm rx fsm descramble and deframe mac interface adc adc timing and frequency correction rake receiver and dpsk demodulation equalizer and cck demodulation dac dac tx filter tx filter modulate/spread frame and scramble radio interface: 2.4 ghz (internal) or 5 ghz (external bcm2060) sync/agc phy registers cofdm
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 6 section 1:functional desc ription document 4318_4318e-ds01-405-r globally available 2.4-ghz unlicensed ism band. with an external transmit power am plifier, it develops full output power per the ieee 802.11b/g specification. the transmit and receive sect ions include all on-chip filtering, mixing, and gain control functions. figure 4: radio functional block diagram r eceiver p ath the bcm4318/bcm4318e have a wide dynamic range, direct conversion receiver. the chip employs high-order on-chip channel filtering to ensure reliable operat ion in the noisy 2.4-ghz ism band. the exce llent noise figure of the receiver makes an external lna unnecessary. leading-edge encore dsp technology is included on bcm4318e for improved receive sensitivity and extended range, enabling whole home coverage. lna lpf lo generation lpf amp rx i tx i calibration control interface control i/f rf output rf input lpf tx q lpf rx q pll xtal sys_clock 20 mhz
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 1:functional description page 7 t ransmitter p ath the bcm4318/bcm4318e include a linear transmitter capable of delivering up to +6 dbm while meeting the ieee 802.11g specification. the output power is adjustable in 0.6-db steps, down to ?15 dbm. baseband data is up-converted directly to the 2.4-ghz ism band. c alibration the bcm4318/bcm4318e feature on-chip ca libration, eliminating process variatio n across components. this enables the device to be used in high-volume applications because calibratio n routines are not required during manufacturing test. these calibration routines are performed periodically in the course of normal radio operation. an example of this is automatic calibration of the baseband filters for op timum transmit and receive performance. c rystal o scillator the recommended configuration for the crystal oscillator including all external components is shown in figure 5. table 2: 20-mhz crystal requirements parameter value frequency 20.000 mhz mode at cut, fundamental load capacitance 16 pf esr 50 ? maximum frequency stability 10 ppm at 25c 10 ppm 0c to +85c aging 3 ppm/year max first year, 1 ppm thereafter drive level 300 w maximum q-factor 40,000 minimum shunt capacitance < 5 pf
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 8 section 1:functional desc ription document 4318_4318e-ds01-405-r figure 5: recommended oscillator configuration crystal 36 pf 36 pf xtal in xtal out 220 ?
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 2:pin assignments page 9 section 2: pin assignments 144-p in bga a ssignments figure 6 and table 3 show the pin as signments for the 144-pin bga device. figure 6: bcm4318/bcm4318e 144-pin top view assignments table 3: 144-pin assignments pin name pin name pin name pin name a1 reserved b1 reserved c1 xtssi2 d1 reserved a2 avdd_dac b2 avss_dac c2 reserved d2 reserved a3 tdo b3 pllgnd c3 reserved d3 reserved a4 tck b4 ext_por c4 reserved d4 reserved a5 rf_disable b5 tr_sw_rx_pu c5 rx_pu d5 reserved a6 vddio b6 gphy_ext_lna_ gain c6 test_se d6 ant_selp a7 sprom_clk b7 sprom_dout c 7 sprom_din d7 ant_seln a8 vddio b8 vss c8 sprom_cs d8 sdio_clk a9 sdio_data_3 b9 sdio_data_2 c9 sdio_cmd d9 d12 a b c d e f g h j k l m 1 2 3 4 5 6 7 8 9 10 11 12
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 10 section 2:pin assignm ents document 4318_4318e-ds01-405-r a10 sdio_data_0 b10 d4 c10 ireq d10 d6 a11 vdd b11 d5 c11 d15 d11 vss a12 d11 b12 d13 c12 a10 d12 a11 e1 rgnd f1 rgnd g1 lnainp h1 lnainn e2 rgnd f2 vddlf g2 vddrx h2 rgnd e3 rgnd f3 rgnd g3 rgnd h3 rgnd e4 avdd_adc f4 avss_adc g4 vss h4 vss e5 tdi f5 jtag_trst g5 plldvdd h5 vss e6 tms f6 tr_sw_tx_pu g6 gpio_1 h6 vdd e7 sdio_data_1 f7 tx_pu g7 d14 h7 gpio_0 e8 d3 f8 vddbus g8 gpio_4 h8 gpio_2 e9 d7 f9 ce0 g9 a2 h9 vddbus e10 ce1 f10 a8 g10 a6 h10 a3 e11 oe f11 a7 g11 d2 h11 a4 e12 a9 f12 wait g12 a5 h12 reg j1 rgnd k1 vddpa l1 pa_out m1 bgref j2 gndpa k2 vddpa l2 vdddr m2 vddtx j3 rgnd k3 gndpa l3 rgnd m3 vddlo j4 rgnd k4 rgnd l4 cp_fb m4 rgnd j5 rgnd k5 vddvco l5 vddpll m5 xtalout j6 rgnd k6 vddpll_ref l6 vddcp m6 xtalin j7 rgnd k7 vdd4w l7 vddxtal m7 rgnd j8 rgnd k8 rgnd l8 rgnd m8 rgnd j9 a1 k9 gpio_5 l9 vdd m9 gpio_3 j10 a0 k10 reset l10 vddio m10 otp_vdd j11 d8 k11 inpack l11 d10 m11 xtal_pu j12d0k12d1l12d9m12we table 3: 144-pin assignments (cont.) pin name pin name pin name pin name
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 2:pin assignments page 11 196-p in bga a ssignments figure 7 and table 4 show the pin as signments for the 196-pin bga device. figure 7: bcm4318/bcm4318e 196-pin top view assignments a b c d e f g h j k l m 1 2 3 4 5 6 7 8 9 10 11 12 13 14 n p
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 12 section 2:pin assignm ents document 4318_4318e-ds01-405-r table 4: 196-pin assignments pin name pin name pin name pin name a1 avss_dac b1 avdd_dac c1 txp_q d1 txn_i a2 fref_2 b2 xtemprssi c2 txn_q d2 txp_i a3 pllgnd b3 plldvdd c3 jtag_trst d3 xnrssi a4 rx_pu b4 tms c4 tck d4 xtssi2 a5 pllvdd b5 tdi c5 ext_por d5 ant_seln a6 tdo b6 tr_sw_rx_pu c6 tr_sw_tx_pu d6 aphy_pa_pd a7 test_se b7 ant_selp c7 aphy_pa_cntrl_ 0 d7 aphy_ext_lna_g ain a8 rf_disable b8 gphy_ext_lna_ gain c8 aphy_sri_e d8 aphy_ext_lna_ pu a9 tx_pu b9 aphy_sri_di c9 aph y_sri_do d9 sdio_data_3/ uart_tx a10 aphy_synth_pu b10 sprom_din c10 sdio_data_1/ uart_dcd d10 cstschg a11 aphy_sri_c b11 sprom_cs c11 pci_int d11 pci_ad_2 a12 sprom_dout b12 sdio_data_0/ uart_cts c12 pci_ad_5 d12 pci_ad_4 a13 sdio_data_2/ uart_dtr b13 sdio_cmd/ uart_rts c13 pci_ad_6 d13 pci_ad_7 a14 pci_ad_0 b14 pci_ad_1 c14 pci_ad_3 d14 pci_cbe_0 e1 xwrssi f1 reserved g1 rgnd h1 rgnd e2 xtssi5 f2 reserved g2 rgnd h2 vddlf e3 avdd_adc f3 rxp_i g3 rgnd h3 rgnd e4 avss_adc f4 rxn_i g4 rxn_q h4 rxp_q e5 uart_rx f5 cmout g5 vddbus h5 vddbus e6 vdd f6 uart_ri g6 vss h6 vss e7 uart_dsr f7 vss g7 vss h7 vss e8 vdd f8 vss g8 vss h8 vss e9 sprom_clk f9 vss g9 vss h9 vss e10 sdio_clk/ uart_clk f10 pci_ad_14 g10 pci_ad_15 h10 pci_ad_16 e11 vesd f11 pci_ad_11 g11 pci_cbe_1 h11 pci_cbe_2 e12 pci_ad_10 f12 pci_ad_13 g12 pci_perr h12 pci_trdy e13 pci_ad_9 f13 pci_par g13 pci_stop h13 pci_clk e14 pci_ad_8 f14 pci_ad_12 g14 pci_serr h14 pci_devsel
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 2:pin assignments page 13 j1 lnainp k1 lnainn l1 rgnd m1 vddpa j2 vddrx k2 rgnd l2 gndpa m2 vddpa j3 rgnd k3 rgnd l3 rgnd m3 gndpa j4 vddbus k4 vddio l4 rgnd m4 rgnd j5 vddbus k5 vddio l5 rgnd m5 vddvco j6 vss k6 vddio l6 rgnd m6 vddpll_ref j7 vss k7 vddio l7 rgnd m7 vdd4w j8 gpio_1 k8 gpio_0 l8 rgnd m8 rgnd j9 vss k9 gpio_6 l9 gpio_5 m9 gpio_2 j10 vss k10 pci_rst l10 otp_vdd m10 gpio_7 j11 pci_ad_17 k11 vdd l11 pci_ad_28 m11 pci_gnt j12 pci_frame k12 pci_ad_20 l12 pci_ad_23 m12 pci_ad_24 j13 pci_ad_18 k13 pci_ad_21 l13 pci_idsel m13 pci_ad_26 j14 pci_irdy k14 pci_ad_19 l14 pci_ad_22 m14 pci_cbe_3 n1 pa_out p1 bgref n2 vdddr p2 vddtx n3 rgnd p3 vddlo n4 cp_fb p4 rgnd n5 vddpll p5 xtalout n6 vddcp p6 xtalin n7 vddxtal p7 rgnd n8 rgnd p8 rgnd n9 gpio_4 p9 gpio_3 n10 pcmcia_sel p10 xtal_pu n11 pci_clkrun p11 pci_pme n12 pci_req p12 pci_ad_31 n13 pci_ad_29 p13 pci_ad_30 n14 pci_ad_25 p14 pci_ad_27 table 4: 196-pin a ssignments (cont.) pin name pin name pin name pin name
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 14 section 3:signal descriptions document 4318_4318e-ds01-405-r section 3: signal descriptions the signal name, type, and description of each pin in the bc m4318/bcm4318e 144-pin fbga package are listed in table 5. the symbols shown under type indicate pin directions ( i/o = bidirectional , i = input, o = output ) and the internal pull-up/ pull-down characteristics ( pu = weak internal pull-up resistor and pd = weak internal pull-down resistor ), if any. see also table 8 on page 31 for resistor strapping options. 144-p in bga d escriptions table 5: bcm4318/bcm4318e 14 4-pin bga signal descriptions signal name pin type description pcmcia/compact flash d0 j12 in/out (16 ma) pcmcia/ compact flash data bus. d1 k12 in/out (16 ma) d2 g11 in/out (16 ma) d3 e08 in/out (16 ma) d4 b10 in/out (16 ma) d5 b11 in/out (16 ma) d6 d10 in/out (16 ma) d7 e09 in/out (16 ma) d8 j11 in/out (16 ma) d9 l12 in/out (16 ma) d10 l11 in/out (16 ma) d11 a12 in/out (16 ma) d12 d09 in/out (16 ma) d13 b12 in/out (16 ma) d14 g07 in/out (16 ma) d15 c11 in/out (16 ma)
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 3:signal descriptions page 15 a0 j10 in pcmcia/compact flash address bus. a1 j09 in a2 g09 in a3 h10 in a4 h11 in a5 g12 in a6 g10 in a7 f11 in a8 f10 in a9 e12 in a10 c12 in a11 d12 in ireq c10 out (16 ma) interrupt request. asserted by the bcm4318/bcm4318e to indicate to the host system that the bcm4318/bcm 4318e requires host software service. the interrupt signal at the interface is routed by the system to one of the in terrupt request signals on the system's internal bus. the signal is negated when no interrupt is requested. ce0 f09 in card enable. the ce0 input enables even-numbered address bytes, and ce1 enables odd-numbered address bytes. a multiplexing scheme based on a0 and ce0 allows 8-bit hosts to access all data on d[7:0], if desir ed. the card enable pins are used to access both common and at tribute memory and to access i/o. ce1 e10 in oe e11 in output enable. used to gate memory read data from memory. hosts must negate the oe si gnal during write operations. wait f12 out (16 ma) extend bus cycle . asserted to delay completion of the memory access or i/o access cycl e then in progress. this pin is also sampled asynchronously at powerup to determine various bus modes. see table 8 on page 31 for details. reg h12 in attribute memory select. when this signal is asserted, access is limited to attribute memory. the reg signal is kept negated for all common memory accesses. inpack k11 out (16 ma) input port acknowledge. asserted when the device is selected and can respond to an i/o read cycle at the address on the address bus. this signal is used by the host to control the enable of any input data buffer between the ca rd and the host system data bus. this signal must be inactive until the card is configured. we m12 in write enable. used for strobing memory write data into memory. reset k10 in card reset. clears the configuration op tion register, placing the device in an unconfigured (memory only interface) state. it also signals the beginning of any additional card initialization. the system must place the reset sig nal in a high-z state during card powerup. the signal must remain high-impedance for at least 1 ms after vddbus becomes valid. table 5: bcm4318/bcm4318e 144-pi n bga signal descriptions (cont.) signal name pin type description
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 16 section 3:signal descriptions document 4318_4318e-ds01-405-r sdio bus interface sdio_data_0 a10 in/out (8 ma) pu sdio data line 0 (see table 9 on page 31). sdio_data_1 e07 in/out (8 ma) pu sdio data line 1 (see table 9 on page 31). sdio_data_2 b09 in/out (8 ma) pu sdio data line 2 (see table 9 on page 31). sdio_data_3 a09 in/out (8 ma) pu sdio data line 3 (see table 9 on page 31). sdio_clk d08 in pu sdio clock (see table 9 on page 31). sdio_cmd c09 in/out (8 ma) pu sdio command line (see table 9 on page 31). sprom bus interface sprom_din c07 in pd sprom data in. must be connected to the dout signal of the sprom. this pin is also used as a strapping option to determine sprom mode. see table 7 on page 30 for details. sprom_dout b07 in/out (4 ma) pd sprom data out. must be connected to the din signal of the sprom (see note below). this pi n is also used as a strapping option to determine sprom mode. see table 7 on page 30 for details. sprom_clk a07 in/out (4 ma) pd serial data clock. must be connected to the serial clock input of the sprom (typically called sk). this pin is also used as a strapping option to determine sprom mode. see table7onpage30 for details. sprom_cs c08 out (4 ma) pu sprom chip select. must be connected to the chip select input of the sprom (typically called cs). this pin is also used as a strapping option to determine sprom mode. see table 7 on page 30 for details. jtag interface tms e06 in pu for normal operation, connect as described in the jtag specification (ieee std 1149.1). othe rwise, if jtag is not used, these pins can be left unconnected (nc), as they have internal pull- ups. tck is typically an 8-mhz clock tck a04 in pu tdi e05 in pu tdo a03 out (8 ma) pu jtag_trst f05 pu gpio interface gpio_0 h07 in/out (8 ma) general purpose interface pins. these pins are high-z on powerup and reset. subsequently, they become inputs or outputs through software control. gpio_1 g06 in/out (8 ma) gpio_2 h08 in/out (8 ma) gpio_3 m09 in/out (8 ma) gpio_4 g08 in/out (8 ma) gpio_5 k09 in/out (8 ma) crystal oscillator xtalout m05 20-mhz xtal output. xtalin m06 20-mhz xtal input . table 5: bcm4318/bcm4318e 144-pi n bga signal descriptions (cont.) signal name pin type description
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 3:signal descriptions page 17 misc. control bgref m01 bandgap reference. connect to gnd through an external 2.87-k ? resistor. cp_fb l04 feedback filter. refer to reference design. ext_por b04 pu external power-on reset. allows connection of the external power-on reset circuit. the internal por can be used as the default without requiring an external circuit. ext_por must be left open for normal operation. rf_disable a05 pu radio disable. asserting this pin low disables the internal 2.4-ghz radio by shutting off everything (including the synthesizer) in the radio other than the oscillator. test_se c06 pu scan enable input. no connect (nc). xtal_pu m11 xtal powerup. pull high for normal operation. reserved signals reserved a01 no connect (nc). reserved b01 no connect (nc). reserved c02 no connect (nc). reserved c03 no connect (nc). reserved c04 no connect (nc). reserved d01 no connect (nc). reserved d02 no connect (nc). reserved d03 no connect (nc). reserved d04 no connect (nc). reserved d05 no connect (nc) 2.4-ghz rf analog interface (ieee 802.11g) ant_seln d07 out (12 ma) antenna select negative. used to drive a diversity switch to select which of the two antennas should be currently in use (for switched diversity operation). ant_seln is the inverse of ant_selp. ant_selp d06 out (12 ma) antenna select positive. used to drive a diversity switch to select which of the two antennas should be currently in use (for switched diversity operation). gphy_ext_lna_ gain b06 out (12 ma) external lna gain control. lnainn h01 in lna differential input. lnainp g01 in lna differential input. pa_out l01 out 2.4-ghz transmitter output. output frequency = 2402?2495 mhz. tr_sw_rx_pu b05 out (12 ma) receive powerup control output for external tr switch. tr_sw_tx_pu f06 out (12 ma) transmit powerup control output for external tr switch. tx_pu f07 out (12 ma) external power amplifier powerup. xtssi2 c01 in 2.4-ghz transmit signal strength indicator. rx_pu c05 out (8 ma) external lna powerup. table 5: bcm4318/bcm4318e 144-pi n bga signal descriptions (cont.) signal name pin type description
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 18 section 3:signal descriptions document 4318_4318e-ds01-405-r 3.3v digital otp_vdd m10 connect to 3.3v digital supply. vddbus f08 vddbus h09 vddio a06 vddio a08 vddio l10 1.8v analog vdd filter group 1 avdd_adc e04 connect this group of pins to a separately filtered 1.8v supply. avdd_dac a02 plldvdd g05 1.8v analog vdd filter group 2 vdd4w k07 connect this group of pins to a separately filtered 1.8v supply. vddpll l05 vddpll_ref k06 vddxtal l07 1.8v analog vdd filter group 3 vddcp l06 connect this group of pins to a separately filtered 1.8v supply. vddlf f02 vddlo m03 vddvco k05 1.8v analog vdd filter group 4 vdddr l02 connect this group of pins to a separately filtered 1.8v supply. vddrx g02 vddtx m02 vdd 1.8v digital vdd a11 connect to 1.8v digital supply. vdd h06 vdd l09 1.8v analog vddpa k01 connect to filtered 1.8v supply. vddpa k02 table 5: bcm4318/bcm4318e 144-pi n bga signal descriptions (cont.) signal name pin type description
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 3:signal descriptions page 19 rf ground gndpa j02 rf gnd. gndpa k03 pllgnd b03 rgnd e01 rgnd e02 rgnd e03 rgnd f01 rgnd f03 rgnd g03 rgnd h02 rgnd h03 rgnd j01 rgnd j03 rgnd j04 rgnd j05 rgnd j06 rgnd j07 rgnd j08 rgnd k04 rgnd k08 rgnd l03 rgnd l08 rgnd m04 rgnd m07 rgnd m08 digital ground avss_adc f04 digital gnd. avss_dac b02 vss b08 vss d11 vss g04 vss h04 vss h05 table 5: bcm4318/bcm4318e 144-pi n bga signal descriptions (cont.) signal name pin type description
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 20 section 3:signal descriptions document 4318_4318e-ds01-405-r 196-p in bga d escriptions the signal name, type, and description of each pin in the bc m4318/bcm4318e 196-pin fbga package are listed in table 6. the symbols shown under type indicate pin directions (i/o = bi directional, i = input, o = output) and the internal pull-up/pull - down characteristics (pu = weak internal pull-up resistor, and pd = weak internal pull-down resistor), if any. see also table 8 on page 31 for resistor strapping options. table 6: bcm4318/bcm4318e 196-pin bga signal descriptions signal name pin type description pci bus and cardbus interface (supports connections to pci and cardbus systems) pci_ad_0 a14 in/out (16 ma) multiplexed 32-bit address and data lines . pci_ad_1 b14 in/out (16 ma) pci_ad_2 d11 in/out (16 ma) pci_ad_3 c14 in/out (16 ma) pci_ad_4 d12 in/out (16 ma) pci_ad_5 c12 in/out (16 ma) pci_ad_6 c13 in/out (16 ma) pci_ad_7 d13 in/out (16 ma) pci_ad_8 e14 in/out (16 ma) pci_ad_9 e13 in/out (16 ma) pci_ad_10 e12 in/out (16 ma) pci_ad_11 f11 in/out (16 ma) pci_ad_12 f14 in/out (16 ma) pci_ad_13 f12 in/out (16 ma) pci_ad_14 f10 in/out (16 ma) pci_ad_15 g10 in/out (16 ma) pci_ad_16 h10 in/out (16 ma) pci_ad_17 j11 in/out (16 ma) pci_ad_18 j13 in/out (16 ma) pci_ad_19 k14 in/out (16 ma) pci_ad_20 k12 in/out (16 ma) pci_ad_21 k13 in/out (16 ma) pci_ad_22 l14 in/out (16 ma) pci_ad_23 l12 in/out (16 ma) pci_ad_24 m12 in/out (16 ma) pci_ad_25 n14 in/out (16 ma) pci_ad_26 m13 in/out (16 ma) pci_ad_27 p14 in/out (16 ma) pci_ad_28 l11 in/out (16 ma) pci_ad_29 n13 in/out (16 ma)
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 3:signal descriptions page 21 pci_ad_30 p13 in/out (16 ma) multiplexed 32-bit address and data lines . pci_ad_31 p12 in/out (16 ma) pci_cbe_0 d14 in/out (16 ma) multiplexed command/byte enables. pci_cbe_1 g11 in/out (16 ma) pci_cbe_2 h11 in/out (16 ma) pci_cbe_3 m14 in/out (16 ma) pci_clk h13 in pci bus clock. pci_clkrun n11 in/out (16 ma) as an input, this signal is driven low to indicate that pci_clk is running; deasserted to indicate a request to stop pci_clk. as an output, this signal is driven low to request that pci_clk continue running. supports mini pci. pci_devsel h14 in/out (16 ma) asserted when a device indi cates it is the destination for the current bus cycle. pci_frame j12 in/out (16 ma) cycle framing signal. pci_gnt m11 in arbitration signal granting access to the bus. pci_idsel l13 in indicates that this device is the target of configuration bus cycles. pci_int c11 od (16 ma) pci inta interrupt signal. pci_irdy j14 in/out (16 ma) master ready signal. pci_par f13 in/out (16 ma) even parity signal for pci_ad[31:0] and pci_cbe [3:0]. pci_perr g12 in/out (16 ma) parity error. pci_pme p11 od (16 ma) used to request a change in the device or system power state. the assertion and deassertion of pci_pme is asynchronous to pci_clk. this signal has an ope n-drain output structure as specified in the pci bus local bus specification , revision 2.2. pci_req n12 in/out (16 ma) arbitration signal requesting access to the bus. pci_rst /reset k10 in pci bus (system) reset. the pin becomes reset for pc card when in pcmcia mode. the system must place the reset signal in a high-impedance state during card powerup. it must remain in high-impedance state for at least 1 ms after vddbus becomes valid. pci_serr /wait g14 in/out (16 ma) pci system error or pcmcia /wait . in pci mode, this pin become s the system error signal. in pcmcia mode, this pin becomes the extend bus cycle (wait). it is asserted by the device to delay completion of the memory or i/o access cycles when in progress. this pin is also used as a strapping option to determine various bus interface modes. see table 8 on page 31 for details. pci_stop g13 in/out (16 ma) cycle stop signal. asserted by the target for retry, disconnect, and abort. pci_trdy h12 in/out (16 ma) target ready signal. table 6: bcm4318/bcm4318e 196-pin bga signal descriptions (cont.) signal name pin type description
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 22 section 3:signal descriptions document 4318_4318e-ds01-405-r pcmcia / compact flash (multifu nction pins shared with pci) d0 p14 in/out (16 ma) pcmcia/compact flash data bus. d1 n13 in/out (16 ma) d2 j12 in/out (16 ma) d3 a14 in/out (16 ma) d4 b14 in/out (16 ma) d5 c14 in/out (16 ma) d6 c12 in/out (16 ma) d7 d13 in/out (16 ma) d8 l11 in/out (16 ma) d9 p13 in/out (16 ma) d10 p12 in/out (16 ma) d11 d11 in/out (16 ma) d12 d12 in/out (16 ma) d13 c13 in/out (16 ma) d14 g13 in/out (16 ma) d15 e14 in/out (16 ma) a0 m13 in pcmcia/compact flash address bus. a1 n14 in a2 m12 in a3 l12 in a4 l14 in a5 k13 in a6 k12 in a7 j13 in a8 g11 in a9 f10 in a10 e13 in a11 f14 in a12 h11 in a13 f13 in a14 g12 in ireq c11 out (16 ma) interrupt request. asserted by the bcm4318/bcm4318e to indicate to the host syst em that the device re quires host software service. the interrupt si gnal at the interface is routed by the system to one of the interrupt request signa ls on the system's internal bus. the signal is negated when no interrupt is requested. pcmcia_sel n10 in bus mode select. this pin is used as a strapping option to determine various bus interface modes. see table 8 on page 31 for details. table 6: bcm4318/bcm4318e 196-pin bga signal descriptions (cont.) signal name pin type description
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 3:signal descriptions page 23 ce0 d14 in card enable. the ce0 input enables even-numbered address bytes, and ce1 enables odd-numbered address bytes. a multiplexing scheme based on a0 and ce0 allows 8-bit hosts to access all data on d[7:0] , if desired. the card enable pins are used to access both common and attribute memory and to access i/o. ce1 e12 in oe f11 in output enable. used to gate memory read data from memory. hosts must negate the oe si gnal during write operations. reg m14 in attribute memory select. when this signal is asserted, access is limited to attribute memory. the reg signal is kept negated for all common memory accesses. inpack n12 out (16 ma) input port acknowledge. asserted when the bcm4318/ bcm4318e is selected and can respond to an i/o read cycle at the address on the address bus. this signal is used by the host to control the enable of any input data buffer between the card and the host system data bu s. this signal must be inactive until the card is configured. we m11 in write enable. used for strobing memory write data into memory. wp n11 write protect. used to reflect the status of the write protect switch of the pc card. if the write protect switch is present, pcmcia_wp is asserted by the card when the switch is enabled, and it is negated when the switch is disabled. if the memory card has no write protect switch, the card connects this line to vss or vddbus, depending on the condition of the card memory. table 6: bcm4318/bcm4318e 196-pin bga signal descriptions (cont.) signal name pin type description
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 24 section 3:signal descriptions document 4318_4318e-ds01-405-r sdio/uart bus interfaces sdio_clk/ uart_clk 1 e10 in pu this pin has dual functions: ? in sdio mode, it becomes the sdio clock (see table 9 on page 31). ? in nonsdio mode, it becomes the input from the uart clock . sdio_cmd/ uart_rts 1 b13 in/out (8 ma) pu this pin has dual functions: ? in sdio mode, it becomes the sdio command line (see table 9 on page 31). ? in nonsdio mode, it becomes the output for the uart request to send line. sdio_data_0/ uart_cts 1 b12 in/out (8 ma) pu this pin has dual functions: ? in sdio mode, it becomes sdio data line 0 (see table 9 on page 31). ? in nonsdio mode, it becomes the uart clear to send line. sdio_data_1/ uart_dcd 1 c10 in/out (8 ma) pu this pin has dual functions: ? in sdio mode, it becomes sdio data line 1 (see table 9 on page 31) . ? in nonsdio mode, it becomes the uart data carrier detect line. sdio_data_2/ uart_dtr 1 a13 in/out (8 ma) pu this pin has dual functions: ? in sdio mode, it becomes sdio data line 2 (see table 9 on page 31) . ? in nonsdio mode, it becomes the uart data terminal ready line. this pin is also used as a strapping option to determine various bus interface modes. see table 8 on page 31 for details. sdio_data_3/ uart_tx 1 d09 in/out (8 ma) (pu/pd) this pin has dual functions: ? in sdio mode, it becomes sdio data line 3 (see table 9 on page 31). ? in nonsdio mode, it beco mes the output for the uart serial transmitter line. this pin is also used as a strapping option to select uart clock mode. see table8onpage31 for details. uart_rx 1,2 e05 in (4 ma) pu uart serial input uart_ri 1,2 f06 in (pu) uart ring indicator uart_dsr 1,2 e07 in (pu) uart data set ready notes: 1. the uart option is only available on bcm4318e. 2. on bcm4318, pins e05, e07, and f06 have no internal connection. table 6: bcm4318/bcm4318e 196-pin bga signal descriptions (cont.) signal name pin type description
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 3:signal descriptions page 25 sprom bus interface sprom_din b10 in pd sprom data in. must be connected to the dout signal of the sprom. this pin is also used as a strapping option to determine sprom mode. see table 7 on page 30 for details. sprom_dout a12 in/out (4 ma) pd sprom data out. must be connected to the din signal of the sprom (see note below). this pin is also used as a strapping option to determine sprom mode. see table 7 on page 30 for details. sprom_clk e09 in/out (4 ma) pd serial data clock. must be connected to the serial clock input of the sprom (typically called sk). this pin is also used as a strapping option to determine sprom mode. see table 7 on page 30 for details. sprom_cs b11 out (4 ma) pu sprom chip select. must be connected to the chip select input of the sprom (typically called cs). this pin is also used as a strapping option to determine sprom mode. see table7onpage30 for details. jtag interface tms b04 in (pu) for normal operation, connect as described in the jtag specification (ieee std 1149.1). ot herwise, if jtag is not used, these pins can be left unconnected (nc), as they have internal pull- ups. tck is typically an 8-mhz clock. tck c04 in pu tdi b05 in pu tdo a06 out (8 ma) pu jtag_trst c03 in pu gpio interface gpio_0 k08 in/out (8 ma) general purpose interface pins. these pins are high-z on powerup and reset. subsequently, they become inputs or outputs through software control. gpio_1 j08 in/out (8 ma) gpio_2 m09 in/out (8 ma) gpio_3 p09 in/out (8 ma) gpio_4 n09 in/out (8 ma) gpio_5 l09 in/out (8 ma) gpio_6 k09 in/out (8 ma) gpio_7 m10 in/out (8 ma) crystal oscillator xtalout p05 20-mhz xtal output. xtalin p06 20-mhz xtal input . misc. control bgref p01 bandgap reference. connect to gnd through an external 2.87-k ? resistor. cp_fb n04 feedback filter. refer to reference design. cstschg d10 out optional cardbus interrupt. indicates a change in the status of the card. this pin is different from pin c11. ext_por c05 in (pu) external power-on reset. allows connection of the external power-on reset circuit. the internal por can be used as the default without requiring an external circuit. ext_por must be left open for normal operation. table 6: bcm4318/bcm4318e 196-pin bga signal descriptions (cont.) signal name pin type description
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 26 section 3:signal descriptions document 4318_4318e-ds01-405-r rf_disable a08 pu radio disable. asserting this pin low disables the bcm4318/ bcm4318e's internal 2.4-ghz radio and the bcm2060 5-ghz radio by shutting off everything (including the synthesizer) other than the oscillator. test_se a07 pd scan enable input. no connect (nc) xtal_pu p10 xtal powerup. pull high for normal operation. reserved signals reserved f01 no connect (nc) reserved f02 no connect (nc) ieee 802.11a inte rface to bcm2060 aphy_ext_lna_ gain d07 out (12 ma) external 5-ghz lna gain control. aphy_ext_lna_pu d08 out (12 ma) external 5-ghz lna powerup enable. aphy_pa_cntrl_0 c07 nc power amplifier control. power control signal to the bcm2060 radio. leave unconnected. aphy_pa_pd d06 out (12 ma) power amplifier powerdown. aphy_sri_c a11 out (4 ma) serial interface clock. connected to the bcm2060 radio. aphy_sri_di b09 out (4 ma) data output to the sri_di pin on the bcm206 0 ieee 802.11a radio device. must be connected to the sri_di pin on the bcm2060 radio. aphy_sri_do c09 in data input from the sri_do pin on the bcm2060 ieee 802.11b/g radio device. must be connected to the sri_do pin on the bcm2060 radio. aphy_sri_e c08 out (4 ma) serial interface enable. connected to the bcm2060 radio. aphy_synth_pu a10 synthesizer powerup. signal to the bcm2060 radio. cmout f05 out common mode voltage output. sets the common mode input voltage of the adc of the radio. rxn_i f04 in receive differential input, in-phase negative component from the bcm2060 radio. rxn_q g04 in receive differential input, quadrature negative component from the bcm2060 radio. rxp_i f03 in receive differential input, in-phase positive component from the bcm2060 radio. rxp_q h04 in receive differential input, quadrature positive component from the bcm2060 radio. txn_i d01 out transmit differential output , in-phase negative component to the bcm2060 radio. txn_q c02 out transmit differential outp ut, quadrature negative component to the bcm2060 radio. txp_i d02 out transmit differential output, in-phase positive component to the bcm2060 radio. txp_q c01 out transmit differential output, qu adrature positive component to the bcm2060 radio. xnrssi d03 in narrowband receive signal strength indicator. input signal from the bcm2060 radio. table 6: bcm4318/bcm4318e 196-pin bga signal descriptions (cont.) signal name pin type description
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 3:signal descriptions page 27 xtemprssi b02 in broadcom corporation temperature sense input from the bcm2060 radio. xtssi5 e02 in transmit signal strength indication from the bcm2060 radio. if used, connect to the output po wer detector of the connected 5-ghz power amplifier. if not used, leave unconnected. xwrssi e01 in wideband receive signal strength indication from the bcm2060 radio. fref_2 a02 in input clock. reference clock from the bcm2060 radio. shared rf signals ant_seln d05 out (12 ma) antenna select negative. used to drive a diversity switch to select which of the two antennas should be currently in use (for switched diversity operation). ant_seln is the inverse of ant_selp. this signal is shared and is used by both the 2.4-ghz (ieee 802.11g) and 5-ghz (iee e 802.11a) rf front ends. ant_selp b07 out (12 ma) antenna select positive. used to drive a diversity switch to select which of the two antennas should be currently in us e (for switched diversity operation). this signal is shared and is used by both the 2.4-ghz (ieee 802.11g) and 5-ghz (ieee 802.11a) rf front ends. tr_sw_rx_pu b06 out (12 ma) receive powerup control output for external tr switch. this signal is shared and is used by both the 2.4-ghz (ieee 802.11g) and 5-ghz (ieee 802.11a ) rf front ends. tr_sw_tx_pu c06 out (12 ma) transmit powerup control output for external tr switch. this signal is shared and is used by both the 2.4-ghz (ieee 802.11g) and 5-ghz (ieee 802.11a ) rf front ends. 2.4-ghz rf analog interface (ieee 802.11g) gphy_ext_lna_ga in b08 out (12 ma) external lna gain control. lnainn k01 in lna differential input. lnainp j01 in lna differential input. pa_out n01 out 2.4-ghz transmitter output. output frequency = 2402?2495 mhz. xtssi2 d04 in 2.4-ghz transmit signal strength indicator. tx_pu a09 out (12 ma) external power amplif ier powerup enable. rx_pu a04 out (8 ma) external lna powerup enable. 3.3v digital otp_vdd l10 connect to 3.3v digital supply. vddbus g05 vddbus h05 vddbus j04 vddbus j05 vddio k04 vddio k05 vddio k06 vddio k07 table 6: bcm4318/bcm4318e 196-pin bga signal descriptions (cont.) signal name pin type description
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 28 section 3:signal descriptions document 4318_4318e-ds01-405-r vesd e11 esd bias. for a pci bus, this pin should be connected to one of the vio pins on the pci connector (pci pins a10, a16, a59, b19, or b59). for mini pci adapters, there are no vio pins on the mini pci edge connector, so these pins should be connected to vddbus. 1.8v analog vdd filter group 1 avdd_adc e03 connect this group of pins to a separately filtered 1.8v supply. avdd_dac b01 pllvdd a05 plldvdd b03 1.8v analog vdd filter group 2 vdd4w m07 connect this group of pins to a separately filtered 1.8v supply. vddpll n05 vddpll_ref m06 vddxtal n07 1.8v analog vdd filter group 3 vddcp n06 connect this group of pins to a separately filtered 1.8v supply. vddlf h02 vddlo p03 vddvco m05 1.8v analog vdd filter group 4 vdddr n02 connect this group of pins to a separately filtered 1.8v supply. vddrx j02 vddtx p02 vdd 1.8v digital vdd k11 connect to 1.8v digital supply. vdd e06 vdd e08 1.8v analog vddpa m01 connect to filtered 1.8v supply. vddpa m02 table 6: bcm4318/bcm4318e 196-pin bga signal descriptions (cont.) signal name pin type description
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 3:signal descriptions page 29 rf ground gndpa l02 rf gnd. gndpa m03 pllgnd a03 rgnd g01 rgnd g02 rgnd g03 rgnd h01 rgnd h03 rgnd j03 rgnd k02 rgnd k03 rgnd l01 rgnd l03 rgnd l04 rgnd l05 rgnd l06 rgnd l07 rgnd l08 rgnd m04 rgnd m08 rgnd n03 rgnd n08 rgnd p04 rgnd p07 rgnd p08 digital ground avss_adc e04 digital gnd. avss_dac a01 vss f07 vss f08 vss f09 table 6: bcm4318/bcm4318e 196-pin bga signal descriptions (cont.) signal name pin type description
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 30 section 3:signal descriptions document 4318_4318e-ds01-405-r s trapping o ptions the pins listed in table 7 and table 8 are asynchronously sa mpled at powerup to determine the various operating modes. each pin has an internal pull-up (pu) or pull-down (pd) re sistor that determines the default mode. to change the mode, connect an external pu to vddio or pd to gnd. sampling occurs within a few milliseconds following internal por or deassertion of external por. after sampling, each pin assu mes the function specified in the signal descriptions table, table 5: ?bcm4318/bcm4318e 144-pin bga signal descripti ons,? on page 14 or table 6: ?bcm4318/bcm4318e 196-pin bga signal descrip tions,? on page 20. vss g06 digital gnd. vss g07 vss g08 vss g09 vss h06 vss h07 vss h08 vss h09 vss j06 vss j07 vss j09 vss j10 table 7: sprom mode and size sprom mode?the sprom pins are asynchronously sampled at powerup to determine sprom mode and size. mode is selected using the sprom_cs and sprom_din pins as follows:. sprom_cs (also called cs) (pu) sprom_din (pd) result 00 sprom present, normal operation 01 sprom present, locked (no writes allowed) 10 reserved 1 1 host mode?sprom absent sprom size?sprom size is selected using the sprom_clk and sprom_dout pins as follows:. sprom_clk (also called sk) (pd) sprom_dout (pd) result 10 16 kbit 01 4 kbit 00 1 kbit table 6: bcm4318/bcm4318e 196-pin bga signal descriptions (cont.) signal name pin type description
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 3:signal descriptions page 31 sdio p in d escriptions figure 8: signal connections to sdio card (sd 4-bit mode) table 8: bus mode configurations bus mode pcmcia_sel pci_serr sdio_data2 (pu) mini/pci 0 x 1 cardbus 0 x 0 sdio 1 0 x pcmcia/compact flash 1 1 x note: x = do not care table 9: sdio pin descriptions sd 4-bit mode sd 1-bit mode spi mode sdio_data_0 data line 0 data data line do data output sdio_data_1 data line 1 or interrupt (optional) irq interrupt irq interrupt sdio_data_2 data line 2 or read wait (optional) rw read wait (optional) nc not used sdio_data_3 data line 3 n/c not used cs card select sdio_clk clock clk clock sclk clock sdio_cmd command line cmd command line di data input bcm4318/bcm4318e sd host clk cmd dat[3:0]
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 32 section 3:signal descriptions document 4318_4318e-ds01-405-r figure 9: signal connections to sdio card (sd 1-bit mode) figure 10: signal connections to sdio card (spi mode) bcm4318/bcm4318e sd host clk cmd data irq rw bcm4318/bcm4318e sd host sclk di do irq cs
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 3:signal descriptions page 33 figure 11: signal connections to pcmcia/compact flash data bus address bus ce0 oe ce1 reg we ireq inpack wait reset compact flash or pcmcia host bcm4318/ bcm4318e
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 34 section 4:electrical char acteristics document 4318_4318e-ds01-405-r section 4: electrical characteristics r ecommended o perating c onditions note: values in this data sheet are design goals and are subject to change based on the results of device characterization. table 10: recommended operating conditions parameter minimum typical maximum units conditions/comments supply voltage ? vddio, vddbus 3.0 3.3 3.6 v ? vddcore, pllvdd, avdd 1.71 1.8 1.89 v logic inputs ? v inh , input high voltage 2.0 v ? v inl , input low voltage 0.8 v logic outputs ? v oh , output high voltage 2.4 v curr ent is determined by the specified pad. ? v ol , output low voltage 0.4 v current is determined by the specified pad.
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 4:el ectrical characteristics page 35 c urrent c onsumption table 11: current consumption parameter typical average current consumption typical peak current consumption units ? 3.3v supply?total a a. for use in power supply design consider ations. specified numbers are worst case va lues for worst case conditions: vcc = 1.89v and 3.6v respectively, ambient temperature = 75c, and absolute highest tx output power (internal attenuators forced to zero). ?75 ma ? 1.8v supply?total a ? 320 ma receive ? receive (54 mbps)?1.8v supply b b. for use in battery life calculations. t he values are typical average currents whil e a packet is being transmitted or received . the values do not represent average current over a specified ti me where there will be periods of no packets. for example, if the device is in power management mode and packets are only being transmi tted/received 50% of the time over a period of time, the average current over that time span would be closer to 50% of the value shown above. in other words, real world typical power consumption will be lower than these values. thes e values are provided to make it easier to calculate time averaged current based on a target application's traffic charac teristics. this only applies in power management mode. if the bcm4318/bcm4318e is not in power management mode then standby rx consumption is the same as consumption during packet reception. also note that these numbers assume typical tx output power under the software driver's tx power control. tbd ? ma ? receive (54 mbps)?3.3v supply b tbd ? ma ? receive (11 mbps)?1.8v supply b tbd ? ma ? receive (11 mbps)?3.3v supply b tbd ? ma transmit ? transmit (54 mbps)?1.8v supply b tbd ? ma ? transmit (54 mbps)?3.3v supply b tbd ? ma ? transmit (11 mbps)?1.8v supply b tbd ? ma ? transmit (11 mbps)?3.3v supply b tbd ? ma power saving ? power save mode, 500 msec dtim? 1.8v supply c c. for use in battery life calculations. these val ues are for current averaged over a 5 second interval. tbd ? ma ? power save mode, 500 msec dtim? 3.3v supply c tbd ? ma
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 36 section 4:electrical char acteristics document 4318_4318e-ds01-405-r l ocal o scillator s pecifications e nvironmental c haracteristics table 12: local oscillator specifications parameter condition minimum typical maximum unit reference input frequency range ? ? 20 ? mhz clock frequency tolerance ? ? ? 20 ppm vco frequency range ? 2412 ? 2484 mhz reference spurs ? ? ? ?34 dbc local oscillator phase noise, single- sided from 1?300 khz offset ? ? ? ?86.5 dbc/hz table 13: environmental characteristics parameter value units conditions/comments ambient temperature (t a ) 0 to 75 coperation storage temperature less than 30 c? relative humidity less than 60 % storage less than 85 % operation esd +1 / ?1.75 kv human body model
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 5:rf specifications page 37 section 5: rf specifications g eneral rf s pecifications r eceiver rf s pecifications note: values in this data sheet are design goals and are subject to change based on the results of device characterization. table 14: general rf specifications parameter condition minimum typical maximum unit tx/rx switch time including tx ramp down ? 5 10 s rx/tx switch time including tx ramp up ? 5 5 s table 15: receiver rf specifications parameter condition minimum typical maximum unit cascaded noise figure ? 6 tbd db maximum receive level a a. when using a suitable external switch. @ 1, 2 mbps ?4 ? ? dbm @ 5.5, 11 mbps ?10 ? ? dbm @ 54 mbps ?10 ? ? dbm input ip3 maximum gain ? ?16 ? dbm minimum gain ? ?2 ? dbm lpf 3-db bandwidth 8 8.5 9 mhz pga dc rejection servo loop bandwidth wb mode ? 1 ? mhz nb mode 120 hz ? 230 khz lpf dc rejection servo loop bandwidth wb mode 500 khz nb mode 120 hz ? 230 khz adjacent channel power rejection at 14-mhz offset ? 38 ? dbc alternate channel power rejection at 25-mhz offset ? 65 ? dbc maximum receiver gain ? 88 ? db gain control step ? 3 ? db/step
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 38 section 5:rf specifications document 4318_4318e-ds01-405-r t ransmitter rf s pecifications table 16: transmitter rf specifications parameter condition minimum typical maximum unit rf output frequency range 2400 ? 2500 mhz output power maximum gain ? +6 ? dbm gain flatness maximum gain ? ? 2 db output ip3 maximum gain ? +18 ? dbm output p1db ? +7 ? dbm output power a a. ieee 802.11(15.4.7.2) requires the minimum transmit power shall be no less than 1 mw at the antenna port. minimum gain ? ?15 ? dbm carrier suppression 15 ? ? dbr tx spectrum mask @ maximum gain fc ? 22mhz < f < fc ? 11mhz ? ? ?30 dbr fc + 11mhz < f < fc + 22mhz ? ? ?30 dbr f < fc ? 22mhz; and f > fc + 22mhz ???50dbr tx modulation accuracy (evm) @ maximum gain 802.11b mode ? 35% 802.11g mode 5% gain control step size ? 0.6 ? db/step i/q baseband bandwidth 802.11b mode 7 8.5 ? mhz 802.11g mode ? 15 ? mhz amplitude balance b b. at a 3 mhz offset from the carrier frequency. dc input ?1 ? 1 db phase balance b dc input ?1.5 ? 1.5 (degrees) baseband differential input voltage shaped pulse ? 0.6 ? vpp tx power ramp up 90% of final power ? ? 2 sec tx power ramp down 10% of final power ? ? 2 sec
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 6:timing characteristics page 39 section 6: timing characteristics pcmcia/c ompact f lash t iming figure 12: pcmcia/compact flash read timing diagram note: values in this data sheet are design goals and are subject to change based on the results of device characterization. 1. shaded area can be high or low. 2. applies to card only when wait is negated by card. however, the host must always provide at le ast this access time before sampling data. 3. applies only when wait is asserted by card. a[11:0] reg ce note 1 ta(a) (2) t c (r) t h (a) note 1 t a (oe) (2) t a (ce) (2) t su (ce) t su (a) oe wait d[15:0] t dis (oe) t dis (ce) t v (wt) t v (a) t h (ce) data valid t en (oe) t w (wt) (3) t v (wt-oe) (3)
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 40 section 6:timing characte ristics document 4318_4318e-ds01-405-r table 17: pcmcia/compact flas h read timing characteristics parameter min max units t c (r) 250 ? ns t a (a) (2) ?200ns t h (a) 20 ? ns t a (ce) (2) ?200ns t su (ce) 0 ? ns t v (a) 0 ? ns t su (a) 20 ? ns t a (oe) (2) ?125ns t h (ce) 20 ? ns t v (wt?oe) (3) ?35ns t w (wt) (3) 0.01 3.0 s t dis (ce) ? 30 ns t en (oe) 10 ? ns t v (wt) 20 ? ns t dis (oe) ? 60 ns see figure 12 for footnotes.
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 6:timing characteristics page 41 figure 13: pcmcia/compact flash write timing diagram 1. shaded area can be high or low. 2. when the data i/o pin is in th e output state, no signals can be applied to the data pins (d[15:0]) by the host system. 3. minimum write pulse width must be met whether or not wait is asserted by card. 4. can be high or low for write timing, but restrictions on oe apply. a[11:0] reg ce note 1 t c (w) note 1 t su (ce-weh) t su (ce) oe we d[15:0] (din) t dis (we) t h (ce) data input established t su (a) t w (we) note 4 note 4 t su (oe-we) note 3 t rec (we) t su (a-weh) t w (wt) t w (wt-we) t h (d) t h (oe-we) t su (d-weh) note 2 d[15:0] (dout ) wait t dis (oe) t en (we) t en (oe) t v (wt)
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 42 section 6:timing characte ristics document 4318_4318e-ds01-405-r sprom t iming table 18: pcmcia/compact flas h write timing characteristics parameter min max units t c (w) 250 ? ns t su (ce-weh) 180 ? ns t su (ce)0?ns t su (a-weh) 180 ? ns t h (ce) 20 ? ns t su (a) 20 ? ns t w (we) 150 ? ns t rec (we) 30 ? ns t v (wt-we) ? 35 ns t w (wt) 0.01 3.0 s t v (wt) 20 ? ns t su (oe-we) 10 ? ns t su (d-weh) 80 ? ns t h (oe-we) 10 ? ns t h (d) 30 ? ns t dis (oe) ? 100 ns t dis (we) ? 100 ns t en (we)5?ns t en (oe)5?ns table 19: sprom timing characteristics signal name period output max output min setup hold sprom_clk 1.92 sec???? sprom_clk falling edge to sprom_dout ?0.5 s0.3 s? ? sprom_clk falling edge to sprom_cs ? 0.5 s0.3 s? ? sprom_clk rising edge to sprom_din ? ? ? 0.5 s ?0.3 s
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 6:timing characteristics page 43 jtag t iming table 20: jtag timing characteristics signal name period output max output min setup hold jtag_tck 125 ns ? ? ? ? jtag_tdi ? ? ? 20 ns 0 ns jtag_tms ? ? ? 20 ns 0 ns jtag_tdo ? 100 ns 0 ns ? ? jtag_trst 250 ns ? ? ? ?
bcm4318/bcm4318e preliminary data sheet 11/09/04 broadcom corporation page 44 section 7:package specifications document 4318_4318e-ds01-405-r section 7: package specifications figure 14: bcm4318/bcm4318e 144-pin fbga
preliminary data sheet bcm4318/bcm4318e 11/09/04 broadcom corporation document 4318_4318e-ds01-405-r section 7:package specifications page 45 figure 15: bcm4318/bcm4318e 196-pin fbga all dimensions and tolerances conform to asme y14.5m-1994.
document 4318_4318e-ds01-405-r broadcom corporation 16215 alton parkway p.o. box 57013 irvine, california 92619-7013 phone: 949-450-8700 fax: 949-450-8710 broadcom ? corporation reserves the right to make changes without further notice to any products or data herein to improve reliability, f unction, or design. information furnished by broadcom corporation is believed to be accurate and reliable. however, broadcom corporation does not assume any liability arising out of the application or use of this information, nor the application or use of any prod uct or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. bcm4318/bcm4318e preliminary data sheet 11/09/04 section 8: ordering information table 21: bcm4318/bcm4318e ordering information part number package ambient temperature bcm4318kfbg 196-pin fbga (lead free) 0 o c to 75 o c BCM4318EKFBG 196-pin fbga (lead free) 0 o c to 75 o c bcm4318skfbg 144-pin fbga (lead free) 0 o c to 75 o c

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